The invention relates to a memory device constructing a memory apparatus and, more particularly, to a memory device suitable for a data processing apparatus of the type such that a large amount of data is supplied from a memory apparatus to a processor. Further, the invention relates to a data processing system configuration comprising a memory apparatus constructed by such a memory device, a memory control apparatus to control the memory apparatus, and processors.
In recent years, in association with the realization of a high operating speed of a microprocessor, the realization of a high operating speed and a high performance of peripheral devices which support the processor is remarkably progressed. For example, as memory devices, "synchronous DRAM", "Rambus-DRAM", "cache DRAM", etc. have been proposed as shown in "The Design of CPU board in these days of 100 MHz", Nikkei Electronics, Vol. 6.8, pages 110-141, 1992 (hereinafter, referred to as a literature 1). Those memory devices are selectively used in accordance with the application part or style in the system.
On the other hand, the performance of the microprocessor is remarkably improved in association with the progress of semiconductor technology and the development of RISC technique. Particularly, a product such that the operating frequency in a chip constructing the microprocessor exceeds 100 MHz has also been proposed owing to the progress of semiconductor technique. Due to the appearance of such a high speed microprocessor, the performance of a system using such a processor is also improved.
However, the following points are pointed out as problems when realizing such a system. Generally, in a process which can be operated in the microprocessor and a cache memory which is arranged therearound and can operate at a high speed, such a high speed performance can be sufficiently effectively used. When the user tries to solve a large scale problem as seen in technical calculations, data to be handled cannot be fully stored in the cache memory, so that a problem such that the performance extremely deteriorates occurs. Namely, since a cache miss occurs, a waiting state of the processor occurs by only a time that is required to transfer the data from a main memory apparatus (or memory apparatus of a lower hierarchy) to the cache, so that the processor enters an idle state and the performance of the system remarkably deteriorates. A degree of such a deterioration in performance has been shown in FIG. 7 and the like of "Proposition of Pseudo Vector Processor by Register Windows and Super Scalar System", The Japan Symposium of Parallel Processing, JSPP'92 collection of papers, pages 367-374 (hereinafter, referred to as a literature 2). According to the pseudo vector processor which has been proposed in the above literature in order to cope with the problem such that the data cannot be fully stored in the cache memory, there is used a device such that the memory accesses to the main memory apparatus (or memory apparatus of the lower hierarchy) are operated like a pipeline, thereby minimizing the deterioration in performance due to the waiting time of the data.
The performance that is required for the main memory apparatus (or memory apparatus of the lower hierarchy) in this case is extremely higher than that of the main memory apparatus (or memory apparatus of the lower hierarchy) of a general microprocessor system using the cache. This is because according to an approach of such a pseudo vector processor, for an increase in latency of the access to the main memory apparatus (or memory apparatus of the lower hierarchy), it is intended to conceal such an increase in latency by using a pipeline structure and it is not intended to reduce an amount of data to be handled. The main memory apparatus (or memory apparatus of the lower hierarchy) for the pseudo vector processor, therefore, needs to have a multi-bank (a group of memory cells which can be independently operated) configuration in which a plurality of memory devices having a high speed interface such as a synchronous DRAM are arranged in parallel in order to realize a large capacity and a high throughput.
In addition to the pseudo vector processors, needs for the main memory apparatus (or memory apparatus of the lower hierarchy) of a large capacity and a high throughput are increasing. As a technique different from the above architecture, there can be mentioned an approach shown in "Examination of Micro Vector Processor Architecture", Information Processing Society of Japan, Research Report 92-ARC-94, pages 17-24 (hereinafter, referred to as a literature 3). According to such an approach, for a problem of decrease in memory access pipeline by an IO pin neck which occurs in the case where the functions of the vector processor are constructed by one chip by realizing a high integration, by executing multi-thread processes of the vector instruction level, an effective deterioration of the memory accessing performance is prevented. In this case as well, a request of the throughput for the main memory apparatus (or memory apparatus of the lower hierarchy) is high. As a system, accordingly, it is necessary to prepare the main memory apparatus (or memory apparatus of the lower hierarchy) with the multi-bank configuration in a manner similar to the pseudo vector processor.
A common point in the systems using the architectures like the above two examples is that it is necessary to cheaply realize the main memory apparatus (or memory apparatus of the lower hierarchy) of a large capacity and a high throughput by an amount of component elements of a small scale. Namely, a memory system has to be provided in accordance with a tendency such that the processor itself intends to realize a small size and low costs. Unless such a memory system can be realized, a balance as a system cannot be obtained and the value of the existence as a system is extinguished.